THEA (Transform Hardware by Evolutionary Algorithms) is a web-based High-Level Synthesis (HLS) framework designed to bridge the gap between high-level software descriptions and optimized hardware architectures. By accepting C code as input, THEA automatically generates synthesizable VHDL output, specifically tailored for FPGA implementation.
At its core, THEA leverages the power of modern compiler infrastructure and metaheuristic optimization. We utilize MLIR and Polygeist to transform source code into intermediate representations. To find the best balance between area, power, and latency, THEA employs Multi-Objective Evolutionary Algorithms (MOEA) via the pymoo library, navigating the complex design space to find the optimal Pareto front for your hardware.
C Source → Polygeist → MLIR
Translating C to structured intermediate representation for hardware analysis.
Evolutionary Algorithms (pymoo)
Searching the design space for optimal trade-offs in area, latency and power consumption.
Structural VHDL Generation
Exporting ready-to-synthesize RTL for Vivado or Quartus.