Joel A. Quevedo, Yazmin Maldonado, "From MLIR to Scheduled CDFG: A Design Flow for Hardware Resource Estimation," in IEEE Embedded Systems Letters, 2025, p. 423-426.
@article{11017650,
author={Quevedo, Joel A. and Maldonado, Yazmin},
journal={IEEE Embedded Systems Letters},
title={From MLIR to Scheduled CDFG: A Design Flow for Hardware Resource Estimation},
year={2025},
volume={17},
number={6},
pages={423-426},
keywords={Hardware;Codes;Delays;Optimization;Estimation;Clocks;Field programmable gate arrays;Power demand;Standards;Scheduling algorithms;Control and data flow graphs (CDFGs);field programmable gate array (FPGA);high-level synthesis (HLS);multilevel intermediate representation (MLIR);scheduling},
doi={10.1109/LES.2025.3575017}}Joel A. Quevedo, Yazmin Maldonado, "In search of efficient hardware designs: A multi-objective journey through MLIR," in Congreso Internacional de Mecatrónica, Control e Inteligencia Artificial (CIMCIA), 2023, p. 117-122.
@inproceedings{quevedo2023search,
title={In search of efficient hardware designs: A multi-objective journey through MLIR},
author={Quevedo, Joel A and Maldonado, Yazmin},
booktitle={Congreso Internacional de Mecatr{'o}nica, Control e Inteligencia Artif},
pages={117-122},
year={2023}}